1. Field of the Invention
The present invention relates to an image display apparatus, and more particularly to an image display apparatus which allows improvement in response speed at data writing for a display in a black level without being affected by constraint in area per pixel.
2. Description of the Related Art
Conventionally, proposals have been made to realize an image display apparatus provided with organic light-emitting diodes (OLEDs) which emit light by recombination of positive holes and electrons injected into a light emitting layer.
FIG. 14 is a diagram of a structure of a pixel-circuit corresponding to one pixel in the conventional image display apparatus. The pixel circuit of FIG. 14 includes an OLED 1, a switching element 2, a driver element 3, a switching element 4, a switching element 5, a gate signal line 6, a gate signal line 7, a source signal line 8, an electroluminescent (EL) power source line 9, and a storage capacitor 1Cs. It should be noted that in a first part of the description on the conventional image display apparatus, the pixel circuit does not include a capacitor 1Ct (shown as surrounded by a broken line).
The OLED 1 has characteristics of emitting light when a potential difference equal to or higher than a threshold voltage is generated between an anode and a cathode to cause an electric current flow therein. Specifically, the OLED 1 includes at least an anode layer and a cathode layer formed from a material such as Al, Cu, and Indium Tin Oxide (ITO), and a light emitting layer formed from an organic material such as phthalcyanine, tris-aluminum complex, benzoquinolinolato, and beryllium complex, and functions to emit light by recombination of positive holes and electrons injected into the light emitting layer.
The switching elements 2, 4, and 5, and the driver element 3 are thin film transistors (TFT).
In the pixel circuit with the above-described structure, in a data writing period the switching elements 4 and 5 are turned ON whereas the switching element 2 is turned OFF. Then, when a programming electric current id is applied via the source signal line 8, the electric current id flows through a path formed by the EL power source line 9, the driver element 3, the switching element 4, and the source signal line 8 in this order. A gate potential VG of the driver element 3 is determined according to the amount of the electric current id flowing along the source signal line 8. Thus, electric charges of an amount corresponding to the gate potential VG are accumulated in the storage capacitor 1Cs.
In a light emitting period following the data writing period, the switching elements 4 and 5 are turned OFF whereas the switching element 2 is turned ON. Then, an electric current id of the same amount as the programming electric current applied in the data writing period flows through the OLED 1. If the amount of electric current id flowing through the source signal line 8 changes in the data writing period, the amount of electric charges accumulated in the storage capacitor 1Cs changes, thereby changing the amount of electric current iOL in the light emitting period to change the luminance of the OLED 1.
When the OLED 1 performs an image display apparatus in a black level, for example, the amount of the electric current id flowing through the source signal line 8, i.e., an amount of an electric current for the black level display, is in the range of 1.5 nA to 29 nA. When the OLED 1 performs an image display apparatus in a white-level, the amount of the electric current id flowing through the source signal line 8, i.e., an amount of an electric current for the white level display, is approximately in the range of a few 100 nA to a few μA depending on an efficiency of the OLED 1, panel luminance, and resolution.
The display in the black level with a small programming electric current id causes rounding of the waveform of id due to a time constant defined by a resistance of the driver element 3 and a parasitic floating capacitance of the source signal line 8, whereby the amount of the electric current id does not reach a predetermined level immediately. To deal with this inconvenience, the conventional image display apparatus is required to have a long data writing period, resulting in a slow response speed.
To eliminate such inconvenience, the gate of the driver element 3 and the gate of the switching element 4 of FIG. 14 may be connected (capacitance-coupled) via the capacitor 1Ct (shown in broken line) to improve the response speed as is conventionally proposed.
With this proposed structure, in the data writing period the switching elements 4 and 5 are turned ON whereas the switching element 2 is turned OFF. Then, the electric current id flows into the source signal line 8. Specifically, the electric current id flows along a path formed by the EL power source line 9, the driver element 3, the switching element 4, and the source signal-line 8, in this order.
In the subsequent light emitting period, the switching elements 4 and 5 are turned OFF whereas the switching element 2 is turned ON. Then, because of the presence of the capacitor 1Ct, the gate potential VG of the driver element 3 changes according to the potential variation on the gate signal line 6.
Variation ΔVG of the gate potential VG here can be represented as ΔVG=ΔVgg×(Cgs+Ct)/(Cgs+Ct+Cs) where Cgs represents a gate-to-source capacitance of the switching element 5. Here, Ct is a capacitance of the capacitor 1Ct, Cs is a capacitance of the capacitor 1Cs, and ΔVgg is a variation in potential on the gate signal line 6.
At the transition from the data writing period to the light emitting period, the potential on the gate signal line 6 rises to increase the gate potential VG of the driver element 3. The amount of increase varies according to the three values of capacitance. Since Cgs is determined based on the size and the structure of the switching element 5, elements that actually control the amount of increase are the capacitor 1Ct and the storage capacitor 1Cs.
Further, the increase in the gate potential of the driver element 3 causes the drain current decrease. The drain current of the driver element 3 drops by an amount corresponding to the variation ΔVG. Hence, the amount of the electric current iOL flowing through the OLED 1 is smaller than a predetermined amount when the switching element 2 is turned ON.
In other words, a larger amount of the electric current id than the predetermined amount is required to be applied to the transistor 3 in the data writing period in order to cause electric current flow of the predetermined amount in the OLED 1 in the light emitting period. The amount of the electric current id can be increased if the storage capacitor 1Cs is smaller or the capacitor 1Ct is larger.
When the storage capacitor 1Cs is smaller, the capacity to retain the electric charges decreases, which makes fluctuation in the gate potential VG of the driver element 3 more likely. Thus, since the smaller storage capacitor 1Cs is not a realistic solution, the larger capacitor 1Ct is preferable.
When the amount of the electric current id flowing through the source signal line 8 increases, an apparent resistance of the driver element 3 can be reduced. Then, the time constant, which is a product of the resistance and the floating capacitance of the source signal line 8, decreases, to shorten the time required for the change of the electric current id to the predetermined amount in the data writing period, whereby the response speed can be improved.
FIG. 15 shows a relation between the electric current id flowing through the source signal line 8 and the electric current iOL flowing through the OLED 1 at various capacitance values of capacitor 1Ct, provided that the amplitude of the gate signal line 6 is 14 V. If the capacitance ratio ((Cgs+Ct)/(Cgs+Ct+Cs)) is 0.03, the amount of the electric current id required to flow through the source signal line 8 is approximately five times the amount of the electric current iOL flowing through the OLED 1. When the capacitance of 1Ct is further increased, the ratio of the electric current id flowing through the source signal line 8 to the electric current iOL flowing through the OLED 1 rises. If the capacitance ratio is 0.8, the amount of the electric current id is 200 times the amount of the electric current iOL, and if the capacitance ratio is increased up to 0.9, the amount of the electric current id is 500 times the amount of the electric current iOL.
With the increase in the amount of the electric current id flowing through the source signal line 8, the resistance of the driver element 3 decreases, and the time required for the attainment of the predetermined amount of electric current is shortened. Hence, a higher capacitance of 1Ct results in more effective improvement of the response speed at data writing for the black level display.
The conventional technique as described above is disclosed, for example, in Japanese Patent Application Laid-Open No. 2003-140612.
As described above, in the conventional image display apparatus, a higher capacitance of 1Ct is more effective for the improvement of the response speed at data writing for the black-level display. The higher capacitance of 1Ct can be realized with a larger area of the capacitor 1Ct.
In the conventional image display apparatus, however, since there is a limit to an area usable for one pixel, the size of the capacitor 1Ct also is under a certain constraint. Hence, though the improvement in response speed is theoretically possible in the conventional image display apparatus, because of the actual manufacturing constraint, a remarkable improvement can hardly be achieved concerning the response speed at data writing for the black-level display.